Product specification File under Integrated Circuits, IC04 January 1995
DESCRIPTION The an 8-bit addressable latch with three address inputs A2), a data input (D), an active LOW enable input (E), an active HIGH clear input (CL), and eight parallel latch outputs to O7). When E and CL are HIGH, all outputs to O7) are LOW. Eight-channel demultiplexing or active HIGH 1-of-8 decoding with output enable operation occurs when CL is HIGH and E is LOW. When CL and E are LOW, the
selected output to O7; determined to A2) follows D. When E goes HIGH, the contents of the latch are stored. When operating in the addressable latch mode CL = LOW), changing more than one bit to A2 could impose a transient wrong address. Therefore, this should only be done while in the memory mode (E = HIGH, CL = LOW).
16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1)
( Package Designator North America PINNING A2 Fig.1 Functional diagram. to O7 address inputs data input enable input (active LOW) clear input (active HIGH) parallel latch outputs
FAMILY DATA, IDD LIMITS category MSI See Family Specifications
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